hardware complexity造句
例句与造句
- presently a lot of pn acquisition schemes have been proposed, but there always is a contradiction between the system performance and the hardware complexity
目前，人们提出的各种扩频序列捕获方案中，始终存在系统性能与硬件复杂度之间的一对矛盾。 - epic defines a new style of architecture that enables higher levels of instruction level parallelism ( ilp ) without unacceptable hardware complexity
epic是一种显性并行指令计算体系结构，主要思想是利用编译器和处理器的协同能力来提高指令级并行度。 - according to the structure of quasi-cyclic ldpc code, we can make a trade-off between hardware complexity and decoding throughput by applying semi-parallel architecture
摘要利用准循环ldpc码的结构特点，使用半并行结构的译码器可以实现复杂度和译码速率的有效折中。 - having made a synthetic consideration of systematic architecture character, we decide to design a common hardware platform in order to decrease the hardware complexity and improve the system stability . the platform can be used in some different sub-systems ( such as was, cs, lr, pdsn, omc, etc . ) with their own software running on it
为降低系统硬件复杂度、提高系统可靠性，并综合考虑系统基于ip的结构特点，将部分硬件子系统单板设计为一个通用的硬件处理平台，该平台可以应用到was、cs、lr、pdsn和omc子系统。 - in this paper a multi-layer neural model is designed based on the multi-scale receptive fields of ganglions in retina . the model can keep watch on the periphery part of a scene while processing the center information of the scene . and why it can balance the hardware complexity, processing precision and computational intensity is analyzed
本文通过模拟人类视网膜神经节细胞的信息处理机制，获得多尺度的感受野分布，设计并实现了在对视野中心区感兴趣的信息进行处理的同时，对周边信息保持一定警觉的层次网络模型，为实现机器视觉系统的实时性和避免巨量计算提供有价值的启示。 - It's difficult to find hardware complexity in a sentence. 用hardware complexity造句挺难的
- in this paper, the common used encoding algorithms and basic finite-field opera-tions algorithms are introduced, and the decoding algorithms such as inverse-free ber-lekamp-massey ( ibm ) algorithm, reformulated inverse-free berlekamp-massey ( ribm ) algorithm and modified euclidean algorithm are analyzed in great detail . based on the ribm algorithm, a modified structure and a pipelined decoder scheme are presented . a tradeoff has been made between the hardware complexities and decoding latency, thus this scheme gains significant improvement in hardware complexity and maximum fre-quency
本文简要介绍了有限域基本运算的算法和常用的rs编码算法,详细分析了改进后的euclid算法和改进后的bm算法,针对改进后的bm算法提出了一种流水线结构的译码器实现方案并改进了该算法的实现结构,在译码器复杂度和译码延时上作了折衷,降低了译码器的复杂度并提高了译码器的最高工作频率。 - in this paper, the common used encoding algorithms and basic finite-field opera-tions algorithms are introduced, and the decoding algorithms such as inverse-free ber-lekamp-massey ( ibm ) algorithm, reformulated inverse-free berlekamp-massey ( ribm ) algorithm and modified euclidean algorithm are analyzed in great detail . based on the ribm algorithm, a modified structure and a pipelined decoder scheme are presented . a tradeoff has been made between the hardware complexities and decoding latency, thus this scheme gains significant improvement in hardware complexity and maximum fre-quency
本文简要介绍了有限域基本运算的算法和常用的rs编码算法,详细分析了改进后的euclid算法和改进后的bm算法,针对改进后的bm算法提出了一种流水线结构的译码器实现方案并改进了该算法的实现结构,在译码器复杂度和译码延时上作了折衷,降低了译码器的复杂度并提高了译码器的最高工作频率。 - the fifth chapter analyzes the fixed-point error of bp-based and normalized bp-based decoding algorithm, and gives the final simulation results of each decoding algorithm . with the simulation results and the considering the tradeoff between hardware complexity and error performance, some key parameters and finite precision analysis for the hardware implementation of ldpc decoder have been performed
第五章对bp-based和normalizedbp-based算法进行了定点仿真,对ldpc译码器的关键参数、硬件实现中的定点量化与字长精度问题进行了深入的研究,给出了对译码器硬件实现具有参考意义的研究结果。 - three decoder architectures, parallel, serial and partially-parallel approaches, are analyzed in this thesis . a kind of novel partially-parallel architecture for decoding ldpc code is proposed . the trade-off between the performance of the decoder, hardware complexity and data throughout can be achieved with this partially-parallel architecture for the random parity check matrix
论文分析了三种不同的译码器结构:并行结构、串行结构以及部分并行结构,并提出了一种新颖的部分并行结构的ldpc译码器,较好地解决了当校验矩阵为随机结构时,译码性能、硬件资源和数据吞吐量平衡的问题。 - the forth chapter focus on the researches of decoding algorithm, first studies the decoding theory and decoding approaches of several iterative message passing algorithms for ldpc code, because of the conflict between simplification and reduced performance of bp decoding algorithm, the thesis analyzes the calculation complexity of each algorithm, and simulates the performance of each algorithm, by considering the tradeoff between hardware complexity and error performance, we get two algorithms which are much easier to implement : bp-based and normalized bp-based decoding algorithm, especially, the last one achieves considerable improvement with almost the same complexity
第四章对ldpc码译码算法进行了深入研究,给出了基于置信传播的几种译码算法的原理和步骤,围绕着bp算法的简化与译码性能下降的矛盾,研究了每一种译码算法的复杂度分析,并相应地给出了每一种译码算法的仿真性能曲线,综合考虑译码性能和译码复杂度两个方面,从而得出了适合硬件实现的算法:bp-based和normalizedbp-based算法,后者在基本不增加译码复杂度的情况下,对译码性能有较大的提高。